FIG. 3(g) shows a cross-sectional view of a polycrystalline silicon(polysilicon) electrode of a prior art charge coupled device (hereinafter referred to as "CCD"). In FIG. 3(g), reference numeral 1 designates a p type silicon substrate. An n.sup.- type layer 2 functioning as a charge transfer channel region is produced on the p type silicon substrate 1. A gate insulating film 3 is produced on the charge transfer region 2. First layer polycrystalline silicon (hereinafter referred to as "polysilicon") gate electrodes 4 are produced at predetermined intervals on the gate insulating film 3. Second layer polysilicon gate electrodes 7 are produced on the first layer polysilicon gate electrodes 4 via the gate insulating film 3.
FIGS. 3(a) to 3(f) show cross-sectional views of the main fabrication processes for producing the device of FIG. 3(g). The production process will be described.
First of all, as shown in FIG. 3(a), an n.sup.- type impurity layer 2 is produced in the p type silicon substrate 1 by ion implantation. Next, as shown in FIG. 3(b), the surface of substrate 1 is oxidized to produce a silicon dioxide film 3 at the surface thereof and a first layer polysilicon film 4 is deposited thereon by chemical vapor deposition (CVD). Next, as shown in FIG. 3(c), photoresist 5 is deposited and a predetermined pattern of the photoresist 5 is produced by a photolithography technique. Then as shown in FIG. 3(d), the first layer polysilicon film 4 and the oxide film 3 are etched using the photoresist as a mask to obtain a predetermined pattern of the first layer polysilicon film 4. Next as shown in FIG. 3(e), a silicon dioxide film 3 is produced on the entire surface by oxidizing the surface of substrate and thereafter a second layer polysilicon film 7 is deposited thereon by CVD. Thereafter, as shown in FIG. 3(f), photoresist 8 is deposited and the photoresist 8 is processed to a predetermined pattern through a photolithography technique. Thereafter, the second layer polysilicon 7 is etched using the processed photoresist 8 as a mask and a double-layer polysilicon gate electrode shown in FIG. 3(g) is completed.
The polysilicon electrode which is produced through the above-described process can be produced such that the interval .DELTA.g.sub.3 between the first layer polysilicon film 4 and the second layer polysilicon film 7 is equal to at the most approximately 3.times.t.sub.ox for the film thickness t.sub.ox of the gate insulating film 3.
Next, the charge transfer operation of CCD having the double-layer polysilicon electrode structure as described above will be described with reference to FIG. 4(a).
FIG. 4(a) shows a manner in which four clock signal phases .phi.1 to .phi.4 are applied to respective electrodes. Here, the four phases as shown in FIG. 5 are used.
At time t=t.sub.1 shown in FIG. 5, it is assumed that transfer charges exist below the two electrodes to which clocks .phi.1 and .phi.2 are respectively applied as shown in FIG. 4(b). In FIG. 4(b), .crclbar.shows transfer charges. Next, clock .phi.3 becomes H from L at time t=t.sub.2, a potential well is also produced below the electrode to which clock .phi.3 is applied and transfer charges are broadened in a region below the three electrodes to which clocks .phi.1, .phi.2, and .phi.3 are respectively applied. At time t=t.sub.3 clock .phi.1 changes to L from H and the manner of movement of transfer charges is as shown in FIG. 4(d). When clock .phi.1 changes to L from H, the potential below the electrode to which clock .phi.1 is applied becomes shallow and the transfer charges move to a region under the electrodes to which clocks .phi.2 and .phi.3 are respectively applied. Then as shown in FIG. 3(g), because the interval .DELTA.g.sub.3 between the first layer polysilicon 4 and the second layer polysilicon gate 7 is approximately 3.times.t.sub.ox, such a large "hollow" that influences the charge transfer is not produced in the potential well at a place between the first layer polysilicon 4 and the second layer polysilicon gate 7, which place is shown by dotted line circle A in FIG. 4(d) and, it is possible to transfer charges without losing charges. As a result, at time t=t.sub.4 shown in FIG. 5, transfer of charges to a region below the two electrodes to which clocks .phi.2 and .phi.3 are respectively applied from a region below the two electrodes to which clocks .phi.1 and .phi.2 are respectively applied is completed as shown in FIG. 4(e).
In the electrode structure produced by the processes as shown in FIGS. 3(a) to 3(g), it is possible to produce the transfer electrode interval .DELTA.g.sub.3 so narrow that charge loss does not occur during the transfer of charges. However, in the structure produced by this process, after completing the process as shown in FIG. 3(g), steps in the polysilicon gate electrodes 7 are produced on the substrate surface and the coverage property of an upper layer film produced later is poor, thereby resulting in deterioration in the insulating property and conductive property of the upper layer film. In addition, while using the upper layer film as a light shielding film, the poor coverage results in insufficient light shielding.
Noticing on these problems, there is an attempt to produce a transfer electrode from only one-layer of polysilicon thereby to remove steps caused by the gate electrode and reduce the poor coverage of the upper layer film.
FIGS. 6(a) to 6(d) show cross sectional views of production processes of a prior art one-layer polysilicon transfer electrode. The production process will be described.
As shown in FIGS. 6(a) to 6(c), an n.sup.- type layer 2 is produced on the substrate 1, an insulating film 3 is produced on the n.sup.- type diffusion layer 2 and further a polysilicon film 4 is deposited on the insulating film 3, and thereafter, photoresist 5 is deposited on the polysilicon film 4 and it is processed to have a predetermined pattern by photolithography similarly as in the prior art device of FIGS. 3(a) to 3(c). Here, the photoresist 5 is patterned to have a minimum gap .DELTA.g.sub.4 as shown in FIG. 6(c) different from the prior art example of FIG. 3(g). The polysilicon film 4 is etched using this patterned photoresist as a mask and as shown in FIG. 6(d). The interval .DELTA.g.sub.4 ' between adjacent gate electrodes is made approximately equal to that of the above-described interval .DELTA.g.sub.4.
The transfer electrode 4 which is produced through these processes has a step which is reduced relative to the case where a transfer electrode is produced using a double-layer polysilicon and can be produced without causing deterioration in the coverage of an upper layer film is produced in a later process. It is also possible to produce an electrode having a low resistance by adopting as material, such as a polycide structure comprising not only polysilicon but polysilicon and tungsten silicide, for the transfer electrode. Then, the electrode can also function as a light shielding film.
In the prior art CCD in which a transfer electrode is produced by one-layer polysilicon, the step is reduced with relative to the case where a transfer electrode is produced using a double-layer polysilicon. On the other hand, the interval between the transfer electrodes which can be realized is determined by the minimum producible feature size of the photoresist and the processing precision of polysilicon using the photoresist as shown in FIG. 6(c). Therefore, the separation interval .DELTA.g.sub.4 ' of polysilicon serving as a transfer electrode after the processing is wider than the transfer electrode interval .DELTA.g.sub.3 =3.times.t.sub.OX (FIG. 3(g)) which is obtained in a case where the double-layer polysilicon is used.
For example, although in the above-described double-layer polysilicon gate electrode structure, when the film thickness t.sub.OX of the gate insulating film 3 is, for example, 0.05 to 0.1 micron, the interval .DELTA.g.sub.3 between adjacent gate electrodes can be below 0.15 to 0.3 micron. In the above-described one-layer polysilicon gate electrode structure, the minimum size .DELTA.g.sub.4 of photoresist 5 which is producible by photolithography is limited to about 0.4 micron and the interval .DELTA.g.sub.4 ' between the gate electrodes using this pattern as a mask is approximately 0.6 micron.
Generally, when a driving clock signal is applied, there is a tendency that the potential level of the n.sup.- type layer 2 which is produced below the gate insulating film 3 increases as the film thickness t.sub.ox of the gate insulating film 3 increases. Accordingly, as shown in FIG. 8, when the interval between the gate electrodes is widened, the difference between the effective gate insulating film thickness t.sub.ox, measured from the edge of the gate electrode 4 and to the n.sup.- type layer 2 between the gate electrodes, and the gate insulating film thickness t.sub.ox, measured between the gate electrode 4 and the n.sup.- type layer 2 increases Therefore, relative to the potential level of the n.sup.- type layer directly below the gate electrode 4, the potential level of the n.sup.- type layer between the gate electrodes 4 is unfavourably increased and a potential level difference .DELTA.E arises between those parts of the n.sup.- type layer 2.
The operation of the charge transfer in a case where a potential level difference .DELTA.E is generated in this way will be described with reference to FIG. 7. As shown in FIG. 7(a), four clock signal phases .phi.1 to .phi.4 are applied and those clock signals shown in FIG. 5 are used for these clocks. It is assumed that transfer charges exist at below the electrodes to which clocks .phi.1 and .phi.2 are respectively applied at time t=t.sub.1 as shown in FIG. 7(b) similarly as in the cases of FIGS. 4(a) and 4(b). A state where the clock .phi.3 becomes H from L at time t=t.sub.2 similarly as in FIG. 4(c) is shown in FIG. 7(c). Thereafter, when the clock .phi.1 changes to L from H at time t=t.sub.3, the transfer charges move to the charge transfer channel region below the electrode to which clock .phi.2 is applied from the charge transfer channel region below the electrode to which clock .phi.1 is applied. Here, because the separation interval .DELTA. g.sub.4 ' between the transfer electrodes 4 is larger than the separation interval between the transfer electrode .DELTA.g.sub.3 =3.times.t.sub.OX in a case where double-layer polysilicon is used, the difference in the potential level directly below the transfer electrode and below a location between the transfer electrodes in the n.sup.- type layer 2 increases and a "hollow" of potential clearly appears at a part which is shown by dotted line circle B in FIG. 7(d). Accordingly, part of charges remain in this hollow during the transfer and a transfer loss arises as shown in FIG. 7(e).